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TAXI
- 基于VHDL的出租车计费器，通过VHDL语言来编程实现计费系统的四个功能块：分频模块，控制模块，计量模块和译码显示模块，最后使用MAX+PLUSII软件来对程序进行仿真，以模拟实现出租车的启动，停止以及等待等过程中的计时，计程和计费功能。-Taxi meter based on VHDL, VHDL language programming through the billing system of the four functional blocks: frequency module, co
001
- vhdl 语言 用计数器实现分频 N分频器的设计-frequency counter vhdl language
vhdl2
- VHDL语言程序 用于偶数分频器 偶数值可修改-VHDL language program for the even-divider values can be modified even
fpq
- 基于VHDL硬件描述语言的分频器的仿真实例与操作步骤-VHDL hardware descr iption language based on the divider of the simulation and the steps
Distributer
- VHDL编写的分频器。用于将50MHz的时钟脉冲分频成一个500Hz的扫描时钟和1Hz的秒脉冲。与我的其它8个模块配套构成一个数字钟。-Programmed with VHDL.A clock distributer which generates a 500Hz scaning clock and a 1Hz second impulse. It is one of my total 9 modules that are used to design a digital clock.
clk_div2
- 本源码是分频器的VHDL,在QUARTUS2下已进行仿真和验证，-The source is the divider of the VHDL, have been carried out under the QUARTUS2 simulation and verification,
VHDL_divider
- 基于VHDL的数控分频器设计及应用.基于VHDL的数控分频器设计，整个过程简单、快捷、可移植性强-VHDL-based design and application of NC divider
deccount2.5
- 2.5分频器设计,用VHDL编写-2.5 divider design using VHDL
09081113
- 简单计数器，分频器，全加器等vhdl程序等-Simple counter, divider, adder vhdl procedures such as
fp15
- 这是一个利用VHDL编写的15分频器，只要在源程序中适当改变参数就可以实现你所要的任意分频。-It is written in a 15 divider using VHDL, as long as the appropriate change in the source parameters can be achieved at any point you want to frequent.
clock
- 数字秒表计数 vhdl 译码器 分频器 计数器 报警器-stopwatch counter
clkdiv
- vhdL语言写的时钟分频器,使用的是二分法的方式实现的功能-that is a vhdl version clock divider
fenpin_m
- 基于VHDL的一种小数分频器，能够实现任意的小数分频-A decimal frequency divider base on VHDL, be able to achieve any decimal frequency divider
VHDL_Divider
- 该文档详细介绍了用VHDL语言实现分数分频器和积分分频器，以及50 占空比的奇数分频和非50 占空比的奇数分频。-This document details the odd fractional divider and integral divider, and 50 duty cycle with VHDL divider and an odd number of non-50 duty cycle divide.
VHDLBasicExperimentSJTU
- 上海交大几个基础VHDL 实验的代码,包括分频器，计数器，七段计数器，状态机，锁存器等-Shanghai Jiaotong University and a few experiments of basic VHDL code, including the frequency divider, timer, seven segment counter, state machines, latches, etc.
div_sim
- 通过使用VHDL语言编写程序实现了分频器的功能-Through the use of VHDL language procedures for the realization of the divider function
2DPSK-linan
- 全数字2DPSK调制解调系统，为VHDL语言。包括512分频器，M序列发生器等。整个过程完成2DPSK的调制与解调。-The full the digital 2DPSK modem system for the VHDL language. Including the 512 divider, the M-sequence generator. The whole process is completed 2DPSK modulation and demodulation.
fenpin11
- 该小数分频器利用VHDL语言，在同一程序中实现了分频比交错、累加器分频两种方式。采用同步时序。-The decimal prescaler use VHDL language, in the same procedure to realization of points staggered, frequency than accumulators points frequency in two ways. The timing synchronization.
VHDLfenpin
- VHDL整数、小数、分数、偶数、奇数、非50 分频器设计-VHDL integer decimal points even odd number not 50 prescaler design
frequency-divider
- 基于VHDL语言实现的数控分频器的设计及其仿真-Based on the numerical control language realization VHDL prescaler design and its simulation